Computers and other information processing systems may include one or more input/output (I/O) memory management units (each, and IOMMU) to provide memory address translations for I/O and other devices to access a system memory, for example, using direct memory address (DMA) transactions. For example, the IOMMU may receive a DMA transaction, including a memory address, from a device, and translate the memory address from the DMA transaction to a memory address in system memory. To improve performance of the system, the IOMMU may include a cache of recent memory address translations, which may be referred to as an I/O translation lookaside buffer (IOTLB). However, in some cases a device may benefit from a larger translation cache than the IOTLB provides. In this case, the device, may include its own cache of recent memory address translations, which may be referred to as a device TLB or an Address Translation Cache (ATC) as described in a Peripheral Component Interconnect Express (PCIe) Address Translation Service (ATS) specification.